The present invention relates to a nonvolatile memory (nonvolatile semiconductor memory device) and a processing system and more particularly to a technique effectively applied for producing a high voltage in a flash memory or an EEPROM (Electrically Erasble Programmable Read Only Memory).
For example, a flash memory or an EEPROM flush includes a voltage boosting circuit as a circuit for producing a boosted voltage which is higher than a power source voltage used for rewriting data.
In this voltage boosting circuit, a Dickson type (parallel type, hereinafter) or a switched capacitor type (serial type, hereinafter) charge pump circuit is known.
As shown in FIG. 33, boosted capacities CB1 to CBn comprising a plurality of depression type MOS (Metal Oxide Semiconductor) transistors are connected to the parallel type charge pump circuit in series. A power source voltage VDD is applied to a first stage boosted capacitance CB1 and thereafter, gradually higher voltages, e.g., 2VDD, 3VDD are applied to the subsequent capacities, and a high voltage (nxe2x88x921) VDD is applied to the final stage boosted capacitance. Here, xe2x80x9cnxe2x80x9d is a boosting rate when no load is applied to the charge pump circuit.
In the case of the serial type charge pump circuit, as shown in FIG. 34, a power source voltage VDD is charged to boosted capacities CB1 to CB1-n and then, all of nxe2x88x921 electrostatic capacities are connected in series. At that time, an nVPP voltage is obtained under a condition that a load current is zero.
An example describing the Dickson type charge pump circuit in detail is Jongshin Shin, xe2x80x9cA New Charge Pump Without Degradation in Threshold Voltage Due to Body Effect,xe2x80x9d IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 8, AUGUST 2000 pp. 1227-1230. Examples describing the switched capacitor type charge pump circuit in detail are Hiroki Morimura, xe2x80x9cA Step-Down Boosted-Wordline Scheme for 1-V Batter Operated Fast SRAM""s,xe2x80x9d IEEE JOURNAL OF SOLID-STATE CIRCUIT, VOL. 33, NO. 8, AUGUST 1998 pp. 1220-1227.
The present inventors have found that a producing technique of the boosted power source voltage using the above-described voltage boosting circuit has the following problem.
In the parallel type, a (nxe2x88x921)VDD voltage is applied to the boosted capacitance at the maximum as described above. On the other hand, a film thickness of an insulating film which can be used in semiconductor integrated circuit device is limited to about two kinds because process stage is complicated and cost is increased.
Therefore, in the case of the thickness of the insulating film of the boosted capacitance, if a voltage exceeds a limit of voltage resistance of a thinner insulating film, all of remaining insulating films must use thick films, and as the number of voltage boosting stages is increased, the number of boosted capacities of the insulating films is increased, so that an area occupied by the boosted capacities is adversely increased.
In a flash memory, especially in a multilevel flash memory in which 2 bit or more information is stored in one memory cell, it is difficult to lower a voltage which is to be applied to a memory cell at the time of writing or erasing even if an outside power source voltage is lowered. In order to generate a necessary voltage to be applied to the memory cell, it is necessary to increase the voltage boosting stages, and if the voltage increasing stages are increased, the area is considerably increased.
Four voltage boosting stages suffice for generating 4V to 7V boosted voltage of power source voltage, but when 18V of power source voltage is to be generated, seven voltage increasing stages are required. Further, since the amount of electric charge per one boosted capacitance is reduced, capacitance value per one boosted capacitance must be increased, and total 3.6 times capacitance values are required as compared with a case in which the boosted voltage is 3V.
The parallel type has a problem that its area is increased because most of the boosted capacities must use thick insulating film. In the case where two kinds of, i.e., 8 nm and 25 nm insulating films are used, it is necessary that a maximum permissible electric field of the insulating film is 5 MV/cm (when SiO2 is used for the insulating film), a 25 nm insulating film is used from third stage when the power source voltage VDD is 1.8V.
On the other hand, in the serial type, all of the insulating films can use thin films. In this type, as described above, after the power source voltage VDD is charged to boosted capacities CB1 to CBnxe2x88x921, all of the nxe2x88x921 boosted capacities are connected in series. Therefore, voltage resistance of the boosted capacitance may be power source voltage VDD.
For example, when a permissible value of the power source voltage is 1.8Vxc2x10.2V and a maximum permissible electric field of the insulating film is 5 MV/cm, the insulating film can be made thin to 4 nm. Therefore, its area can be reduced.
However, the serial type has the following problem.
In the charge pump circuit, it is important to reduce a ratio of input current and output current as small as possible. In an ideal n-times voltage charge pump circuit, the following equation is established between input current IPP and output current IOUT:
IDD=nIOUTxe2x80x83xe2x80x83(equation 1) 
In an actual case, however, redundant current flows due to a dispersion layer of a MOS capacitance, capacitance against substrate of a well, or parasitic capacitance in a drive circuit. Especially in the serial type, since n-times voltage of a power source voltage VDD is applied to a parasitic capacitance Cp parasitized to the boosted capacitance. Therefore, there is a problem that waste current discharged by them becomes greater than that of the parallel type, and the input and output current ratio becomes much greater than an ideal value n.
It is an object of the present invention to provide a nonvolatile memory and a processing system in which a voltage generating section for producing a high voltage can produce high voltage efficiently, and a layout area of a semiconductor chip can be reduced.
The above and other objects and new features of the present invention will be apparent from the description of this specification and accompanying drawings.
An outline of a representative invention disclosed in this application will be explained briefly below.
The present invention provides a producing technique of a high voltage in a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device comprises a memory array having a plurality of nonvolatile memory cells, a control section, and a voltage producing section for supplying a predetermined voltage to be supplied to the nonvolatile memory cell, wherein the voltage producing section comprises an operation signal producing section for producing a predetermined voltage to be applied to the memory cells in each of the operations in accordance with control from the control section, and a plurality of voltage generating sections, the operation signal producing section produces various operation signals to be supplied to the plurality of voltage generating sections, the voltage generating section comprises a serial type first charge pump circuit for producing a boosted voltage based on a first operation signal, a serial type second charge pump circuit for producing a boosted voltage based on a second operation signal, and an equalizer for short-circuiting parasitic capacities of the first and second charge pump circuits based on a third operation signal during a floating state of the corresponding parasitic capacities parasitized to the boosted capacities of the first and second charge pump circuits when the boosted voltage produced by the first or second charge pump circuit is output.
An outline of another invention of this application will be described briefly.
1. A Nonvolatile Semiconductor Memory Device:
A nonvolatile semiconductor memory device comprises a memory array having a plurality of nonvolatile memory cells, a control section, and a voltage producing section for supplying a predetermined voltage to be supplied to the nonvolatile memory cell, wherein the voltage producing section comprises an operation signal producing section for producing a predetermined voltage to be applied to the memory cells in each of the operations in accordance with control from the control section, and a plurality of voltage generating sections, the operation signal producing section produces various operation signals to be supplied to the plurality of voltage generating sections, the voltage generating section comprises a third charge pump circuit having a parallel type parasitic capacitance provided at its preceding stage and a plurality of serial type pump circuits connected to its following stage, the third charge pump circuit producing a boosted voltage based on the first operation signal, a fourth charge pump circuit having a parallel type parasitic capacitance provided at its preceding stage and a plurality of serial type pump circuits connected to its following stage, the fourth charge pump circuit producing a boosted voltage based on the second operation signal, and an equalizer for short-circuiting parasitic capacities of the first and second charge pump circuits based on a third operation signal during a floating state of the corresponding parasitic capacities parasitized to the boosted capacities of the first and second charge pump circuits when the boosted voltage produced by the third and fourth charge pump circuit is output.
2. A Processing System:
A processing system comprises a nonvolatile memory section and a central processing unit, the central processing unit can carry out a predetermined processing, and can give operation instructions to the nonvolatile memory section, wherein the nonvolatile memory section comprises a plurality of nonvolatile memory cells for storing information, and a voltage producing section, the voltage producing section comprises an operation signal producing section and a plurality of voltage generating sections, the voltage generating section comprises, a third charge pump circuit having a parallel parasitic capacitance provided at its preceding stage and a plurality of serial pump circuits connected to its following stage, said third charge pump circuit producing a boosted voltage based on the first operation signal, a fourth charge pump circuit having a parallel parasitic capacitance provided at its preceding stage and a plurality of serial pump circuits connected to its following stage, said fourth charge pump circuit producing a boosted voltage based on the second operation signal, and an equalizer for short-circuiting parasitic capacities of said first and second charge pump circuits based on a third operation signal during a floating state of the corresponding parasitic capacities parasitized to the boosted capacities of said first and second charge pump circuits when the boosted voltage produced by said third or fourth charge pump circuit is output.